Objective

Validate and characterize the integrated AC-DC converter to confirm compliance with electrical, functional and protection specifications. Verify SPI programmability, NVM programming and behavior across PVT corners, and confirm dynamic buck performance and efficiency up to 5 W.

Primary Targets
  • Stable DC regulation across input range (24–277 VAC)
  • Protection tests: OVP, UVP, OCP, OTP per register config
  • Buck switching performance 200 kHz–2 MHz, load transient & efficiency
Deliverables
  • Final ATE test program (DC, Functional, SPI/NVM)
  • Characterization report (Efficiency, Line/Load/Temp sweeps)
  • Correlation vs bench validation; ESD/LU and HTOL qual programs

Device Overview

High-voltage CMOS AC-DC converter integrating a pre-regulator (AC charge-injection & hold), switching buck regulator, multiple linear regulators (3.3 V, 5 V), on-chip reference/bias, and protection blocks. Programmable via SPI with NVM for configuration storage.

  • Pre-Regulator handling AC-line hold and charging
  • Buck switching regulator (200 kHz–2 MHz)
  • Multiple linear LDOs (3.3 V, 5 V) and integrated references
  • Protection: OVP, UVP, OCP, OTP; SPI programmable thresholds
  • On-chip NVM for trim and configuration

Test Platform & Setup

ATE Platform: Chroma 3650 with PVI-100 rider card. Current production uses single-site test; design supports up to 4-site parallelism for future production scaling. Hardware includes a load board and daughter-card for final test and bench correlation. Qualification covers –40°C to +125°C.

Measurement Domains
  • High-voltage AC line & pre-regulator validation
  • Low-voltage buck and linear regulator checks
  • Digital SPI interface and NVM programming

Test Categories

A. DC & Power Validation

IDDQ in different modes, pin leakage, absolute maximum tests, PREG1/PREG2 regulation checks across voltages and temps.

B. Functional Tests

SPI read/write verification, NVM auto-read/write validation, register persistence after power cycles.

C. Protection Tests

OVP, UVP, OCP, and OTP trip point verification matching programmable thresholds (per spec tables).

D. Dynamic Performance

Buck switching frequency (200 kHz–2 MHz), ramp slope, load-transient response and full efficiency sweeps 0–5 W.

E. NVM & Trim Verification

Program/readback NVM bits for buck/pre-reg trims, oscillator/ramp generator trims and verify across temp.